Parallel Programming for FPGAs

2018年5月20日 | By News | Filed in: News.

One of the best features of using FPGAs for a design is the inherent parallelism. Sure, you can write software to take advantage of multiple CPUs. But with an FPGA you can enjoy massive parallelism since all the pieces are just hardware. Every light switch in your house operates in parallel with the others. There’s a new edition of a book, titled Parallel Programming for FPGAs that explores that topic in depth and it is under the Creative Commons license. In particular, the book focuses on using Vivado HLS instead of the more traditional Verilog or VHDL.

HLS allows a designer to express a high-level algorithm in C, C++, or SystemC. Given a bit more information, HLS will convert that into an FPGA configuration. That doesn’t mean, though, that you can just cut and paste ordinary C code. HLS has several restrictions due to the fact that it is compiling to logic gates, not lines of code. Actually, it also generates Verilog or VHDL, but if you do it right, that should be transparent to you.

After the introduction, the book is more like a series of monographs on very specific topics, but the depth of each is very impressive. There’s plenty of DSP examples, of course. There’s also general math, so if you ever wondered how to compute a sine or cosine in an FPGA, read chapter 3.

Chapter 9 with its discussion of video processing will be of great interest, and there are discussions of sorting algorithms and Huffman encoding, too.

HLS is a great tool, but we fear it will confuse people even further. FPGAs don’t run software (unless you build a CPU on one), but many people mistake HDL descriptions for software because they look superficially similar. HLS makes it even worse because it really is C or C++ code. But it doesn’t compile to object code like a normal program. Of course, that’s only a problem when you have to convince a client or a manager that you can’t apply certain software methodologies to FPGA development. For actual use, HLS is great and can simplify development greatly.

As an example of what HLS looks like, here’s an FFT which, admittedly, uses some other C functions. But it is much more intuitive — especially if you are a programmer — than similar code would be in VHDL or Verilog.

#pragma HLS dataflow
DTYPE Stage1 R[SIZE], Stage1 I[SIZE];
DTYPE Stage2 R[SIZE], Stage2 I[SIZE];
DTYPE Stage3 R[SIZE], Stage3 I[SIZE];
bit reverse(X R, X I, Stage1 R, Stage1 I);
fft stage one(Stage1 R, Stage1 I, Stage2 R, Stage2 I);
fft stages two(Stage2 R, Stage2 I, Stage3 R, Stage3 R);
fft stage three(Stage3 R, Stage3 I, OUT R, OUT I);

The book is meant to be a university text, so it isn’t light reading. Still, it is a great treatment of the topic and the price is right.

If you want a more gentle introduction to classic FPGA development we have that. There are other ways to do C to FPGA, too.


via Hack a Day

May 19, 2018 at 05:00PM


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