Just how did IBM squeeze 1024 Kintex UltraScale FPGAs into a data center server? 32 FPGAs/sled, 2 sleds/chassis, 16 chassis/rack

2017年9月20日 | By News | Filed in: News.

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Sounds like a riddle, doesn’t it? How do you squeeze 1024 Xilinx Kintex UltraScale FPGAs plus 16Tbytes of DDR4 SDRAM into a standard 19-inch data-center rack and why would you do that? I can’t tell you how you would do it but I can tell you how IBM Research did it. They started with the design of the FPGA card, mounting a Kintex UltraScale KU060 FPGA on a PCIe card along with a big chunk of DDR4 SDRAM and a Cypress Semiconductor PSOC with an on-chip ARM Cortex-M3 processor for housekeeping over USB. They also instantiated a 10GBASE-KR 10Gbps backplane Ethernet NIC in the FPGA. (This is definitely an application where you want those bulletproof Xilinx UltraScale MGT SerDes transceivers.)

 

The card looks like this:

 

 

 

IBM Research Kintex UltraScale FPGA Server Card.jpg 

 

 

 

Next, IBM Research stuffed 32 of these cards into a half-rack “sled”—a passive carrier board that electronically aggregates the boards with an Intel FM6000 multi-layer switch chip that funnels the 10GbE connections into eight 40GbE optical connections. Then, they bolted two sleds into a 2U, 19-inch rack chassis that connects to the rest of the rack via the 16 40GbE ports on the north side of the Ethernet switches. Install 16 of these chassis into a rack, add 50kW of power and water cooling, and there you have it.

 

What do you have? Allow me to quote from the conclusion of the IBM paper titled “An FPGA Platform for Hyperscalers,” presented at last month’s IEEE Hot Interconnects conference in Santa Clara:

 

“…we first compared the network performance of our disaggregated FPGA with that obtained from   bare-metal servers, virtual machines, and  containers. The results showed that standalone disaggregated FPGAs outperform them in terms of network latency and throughput by a factor of up to 35x and 73x, respectively. We also observed that the Ethernet NIC integrated within the FPGA fabric was consuming less than 10% of the total FPGA resources.”

 

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September 20, 2017 at 07:09AM


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