By Adam Taylor
Note: Adam Taylor just cannot stop working with or writing about Xilinx devices (nor would we want him to). So here’s the first instalment of his new sub-series about the Zynq UltraScale+ MPSoC.)
Over the last three years, we have used this blog to look at and will continue to look at how we can use the Zynq-7000 SoC in our designs. However, the next generation Zynq, the Zynq UltraScale+ MPSoC, is now available and it would be remiss if we did not also cover how to use this new device and the Avnet UltraZed board in our designs and applications as well. So, welcome to the UltraZed edition of the MicroZed Chronicles.
Avnet UltraZed board on Carrier Card
Before we delve into the Avnet UltraZed board, which we are going to be using to explore this device, I want to spend some time explaining the internals of the Zynq UltraScale+ MPSoC device itself. Of course, this is just an overview and we will be looking more in depth at all aspects of the device as this series continues.
The Zynq UltraScale+ MPSoC is a heterogeneous processing platform which, like the Zynq-7000 SoC, combines a Processing System (PS) with Programmable Logic (PL). However, both PS and PL in the Zynq UltraScale+ MPSoC are significantly more capable.
Within the Zynq UltraScale+ MPSoC’s PS, we find the following main processing elements (I say main as there are others which will be introduced as well):
- Quad-core or dual-core 64-bit ARM Cortex A53 processors within the Application Processing Unit (APU)
- Dual 32-bit ARM Cortex R5 processors within the Real-Time Processing Unit (RPU)
- Mali-400 Graphics Processing Unit (GPU) – Within the Zynq UltraScale+ EG and EV devices
These processing elements connect via a central interconnect to the MIO peripherals and other functions and interfaces within the PS. The MIO contains the same SPI, UART, I2C, CAN, etc. that are familiar to developers using the Zynq-7000 SoC. For configuration and storage, we can use SD/eMMC, Quad SPI or NAND Flash, also provided by the MIO, while high-speed system communication is provided via multiple GigE and USB 3 interfaces.
Zynq UltraScale+ MPSoC Block Diagram
The APU connects to the central interconnect via the System Memory Manager Unit (SMMU) and the Cache Coherent Interconnect (CCI) while the RPU connects to it via the low-power domain switch and the SMMU.
Which brings us nicely to the MPSoC power domains. There are four in total; three within the PS; and one in the PL:
- Battery Power Domain (BPD) – Lowest power mode, allows the maintenance of information when the power is removed, for instance in the BBRAM and RTC.
- Low Power Domain (LPD) – Mid power mode of the PS, powering a subset of the PS including the RPU.
- Full Power Domain (FPD) – Highest power mode of the PS with all the components of the PS powered up. In this mode we can still have the PL powered down if desired.
- PL Power Domain (PLPD) – Final Power mode which powers the PL.
We should remember that in these modes, the power dissipation will depend upon which of the components within the domain are currently being used and their operating frequency. These power domains are operated under the control of the Platform Management Unit (PMU). The PMU is a triple-redundant processor. It controls the power-up, reset and system monitoring for the Zynq UltraScale+ MPSoC. The PMU is a very interesting resource as it is also capable of running user-developed programs to provide more detailed system monitoring for safety and security applications.
When it comes to executing our application(s), we can use DDR3/4 SDRAMs or their low-power versions under the control of the integrated DDR controller. Data paths to this controller are directly from the RPU or the APU via its Cache Coherent Interconnect, while the PL, DMA controller, and Display Port Interfaces can be switched between as required.
So far, we have only examined the PS. The PL of the Zynq UltraScale+ MPSoC consists of next-generation programmable-logic fabric from either the Kintex UltraScale+ or Virtex UltraScale+ FPGA families, which include UltraRAM, Block RAM, and DSP48E2 slices. Depending upon which of the Zynq UltraScale+ MPSoC devices you select, you will find increased connectivity solutions like PCIe, Interlaken, GTH and GTY transceivers within the PL. In the EG device family, you will also find an H.265 / H.264 Video Codec.
Like the Zynq-7000 SoC, the PS is the device master and configures the PL after power-up and initialization. The main method communication between the PL and the PS is also very similar and uses AXI Interfaces in both directions. Either the PL or the PS can be the AXI master. Depending upon the interface selected, these can be Cache- or I/O-Coherent or non-coherent; with data widths of 32, 64 or 128 bits.
Additional interfaces between the PS and the PL include:
- PS Clocks – Four frequency-programmable clocks from the PS to the PL
- Interrupts – PL-to-PS and PS-to-PL interrupts
- EMIO Interfaces – Extended MIO made available from selected MIO components to the PL
- Stream Interfaces – Dedicated stream interfaces for the GigE and Display Port components
- PMU PL Interface – Dedicated signals for controlling and monitoring the PL via the PMU
- Events – Bidirectional event signalling between PS and PL including wait for event and wait for interrupt, FPD and LPD events
- DMA signals – Dedicated signals required for DMA transfers between PS and PL
Having briefly introduced the Zynq UltraScale+ MPSoC architecture, next week we will look at the UltraZed board and begin to build our first example.
You can find an overview of the different Zynq UltraScale+ MPSoC families here.
The in depth Zynq UltraScale+ MPSoC technical reference manual is available here.
via Xcell Daily Blog articles http://ift.tt/2fBJIws
January 31, 2017 at 11:54PM