Xilinx announces first customer shipment of Virtex UltraScale+ devices based on TSMC’s 16nm FF+ process

2016年1月29日 | By News | Filed in: News.

Source: https://forums.xilinx.com/t5/Xcell-Daily-Blog/Xilinx-announces-first-customer-shipment-of-Virtex-UltraScale/ba-p/678587

Xilinx just announced first customer shipments of high-end Virtex UltraScale+ devices based on TSMC’s 16nm FF+ (enhanced FinFET) process technology. As TSMC states on its 16FF+ Web page, “… the 16nm technology offers substantial power reduction for the same chip performance.” The Virtex UltraScale+ FPGAs are Xilinx’s biggest system chips yet, with big-system features including several million logic cells; as much as 455Mbits of on-chip Block RAM including UltraRAM (really big Block RAM); integrated 100G Ethernet MAC with RS-FEC, 150G Interlaken, and PCIe Gen3 x16 and PCIe Gen4 x8 cores; and as many as 128 32.65Gbps SerDes ports with an aggregate bandwidth that tips the scales at a mind-boggling 8.4Tbps.

Think these chips are “glue”? Fuhgettaboutit!

These chips are for designing and building large, robust systems with leading-edge performance (2x to 5x more system-level performance/Watt than you get with 28nm devices). Take a look at some of the reference designs listed on the Virtex UltraScale+ Web page:

That first design, the 24-channel Radar beamformer? You get a 66% reduction in BOM cost and a 66% reduction in total power consumption by switching from a Kintex UltraScale device to a Virtex UltraScale+ device. Those figures alone should make you want to take a look. (Caveat: Your mileage may vary. Every system is different.)

Today’s announcement also talks about this Virtex UltraScale+ device shipment being another proof point, representing “three consecutive generations of leadership technology at 28nm, 20nm, and now at 16nm.” Frankly, that’s from an IC-design perspective. As a system designer, I prefer to think of it this way—today’s announcement is about shipping the first devices in the ninth consecutive, distinct product line that Xilinx has developed with TSMC using three leading-edge IC process generations. Those nine distinct product lines include seven FPGA families, the groundbreaking Zynq All Programmable SoC family, and the even-more-capable Zynq UltraScale+ MPSoC family:

Although it goes without saying, I’ll say it anyway: This sort of thing just does not happen without an immensely strong semiconductor manufacturing partner and that phrase aptly describes TSMC, which has helped Xilinx pull in schedules and ship devices early—beating schedules that were already overly optimistic.

Today’s announcement also says (so I’m not giving anything away here) that more than 100 Xilinx customers are already actively developing designs based on devices in the three UltraScale+ device portfolios. That’s a better, more credible way of telling you that there is already tool support for UltraScale+ devices baked into the latest shipping version of the Vivado Design Suite HLx editions (2015.4), which include Vivado HLS (high-level synthesis).

It’s also a way of letting you know that if you’re not already designing your next system with Xilinx UltraScale+ devices, then it looks like you could already be trailing your competition. ‘Nuff said.


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