The popular hacker site Hackaday.com recently covered the Xcell Daily blog post “C-level Synthesis for Spartan-6 FPGAs? Yes you can. No extra charge” and Mike Field of Hamsterworks in New Zealand posted a lengthy comment on the Hackaday post with advice on using Vivado HLS:
“I am slowly playing around with this. It is well worth trying. The guts are pretty simple to explain. You write your C code and test it, in a very simple IDE-like environment. You can write standard C test benches to verify your code works. Then you convert it to HDL logic.
The steps are:
- The HLS tool breaks the codes into “pseudo machine code”, each of which can be implemented with FPGA logic. (e.g. FMULT, ADD, INC)
- Loops are analyzed, and as directed by analysis pragmas can be unrolled. Loops that are not fully unrolled become the throughput choke points – e.g. if a complex multiply takes 30 cycles, and you do it up to 256 times the latency will be between 30 and 7,680 cycles. However, if you unroll it 256 times (with the #pragma HLS_PIPELINE directive) it will become a 7680 stage pipeline which can accept new data every cycle.
- Function calls can cause either a separate instance of the logic required to support the sub-function to be created, or can cause some sort of arbitrated interface to be created for accessing a single instance of the function’s logic.
- A schedule for how these pseudo machine code operations can be chained is generated, and takes into account the desired performance constraints (e.g. clock speed).
- The code generator then maps the pseudo machine code operations onto logic, and emits HDL code (e.g. Verilog or VHDL), with a simple stream-line interface for parameters and return values. It seems you can also add other pragmas or datatypes to make AXI interfaces if desired – I haven’t looked at that yet.
- You can then take this code/IP block and include it in your traditional HDL project.
When it comes to optimizations there are a whole lot of custom datatypes (e.g. n-bit integers, fixed precision integers…) that can be used, but I haven’t really got that far into it yet. Using these appropriately is important for generating minimal logic and increasing design performance. Pointer support is also a bit variable – contention for the memory interface can be an issue.
I’ve got a thread in the Microcontrollers and FPGAs section on EEVBLOG that I’m posting my limited experience if anybody is still interested…”
Further down in the comments, reader Darren (Colin O’Flynn of NewAE Technology in Halifax, Nova Scotia) posted a 26-minute YouTube video on how to use Vivado HLS to generate HDL for an FIR filter and then feed the resulting HDL code into ISE to compile a configuration for a target FPGA. His target is actually a Xilinx Spartan-3 FPGA: