You’ve been waiting for this. The Zynq UltraScale+ MPSoC Technical Reference Manual (UG1085) is now online and available for download. It contains all of the details you’ve wanted to know about the Zynq UltraScale+ MPSoC including this detailed block diagram:
Like the original (and very successful) Zynq-7000 SoC, the Zynq UltraScale+ MPSoC has two major sections: the PS (Processor System) and the PL (Programmable Logic) section. The Zynq UltraScale+ MPSoC PS block is significantly more powerful than the Zynq-7000 SoC’s PS and includes three major software-programmable processing units:
- An ARM Cortex-A53 APU (Application Processing Unit), a quad-core, multiprocessing CPU based on the 64-bit ARM v8 architecture. (See the top, middle of the diagram.)
- An ARM Cortex-R5 RPU (Real-time Processing Unit), a real-time processor in a dual-core configuration based on the 32-bit ARM v7 architecture. The RPU has dedicated, tightly coupled memory (TCM) and is capable of operating the dual cores in lock-step for designs with functional safety requirements. (See the top left in the diagram.)
- An ARM Mali-400 GPU (Graphics Processing Unit) with integrated pixel and geometry processors and with its own 64Kbyte L2 cache. (See the top right in the diagram.)
The Zynq UltraScale+ MPSoC PS has four high-speed serial I/O (HSSIO) interfaces (look on the right in the above diagram) that support the following widely used industry protocols:
- Integrated block for PCIe base specification, version 2.1 compliant.
- SATA 3.1 specification-compliant interface.
- DisplayPort interface—implements a DisplayPort source-only interface with video resolution to 4k x 2k pixels.
- USB 3.0, 5Gbps interface.
- 1Gbps Ethernet interface.
Zynq UltraScale+ MPSoCs also have a platform management unit (PMU)—which manages all the power sequencing within the device, implements power safety routines to detect tampering with PS voltage rails, performs logic built-in self-test (LBIST), and responds to a designer-driven power management sequence—and a Configuration Security Unit (CSU) that manages secure booting and on-chip security. (See the bottom of the block diagram for the PMU and CSU.)
If you look carefully at the bottom right of the block diagram, you’ll see the PL section—definitely not drawn to scale. The Zynq UltraScale+ MPSoC PL is based on the Xilinx UltraScale FPGA architecture, which consists of enhanced versions of the familiar Xilinx FPGA resource blocks (logic cells, BRAM (block RAM), DSP slices, and MGTs (multi-Gbps transceivers) as well as the UltraScale architecture’s new UltraRAM (jumbo-sized BRAM). The Zynq UltraScale+ MPSoC PL contains additional resources such as integrated (hardened) blocks for high-speed PCIe, 100G Ethernet, and Interlaken. Of course, the number and type of resources included in the Zynq UltraScale+ MPSoC PL depends on which family member you choose.
There’s way too much to cover in this blog post, which is why there’s a 905-page Zynq UltraScale+ MPSoC Technical Reference Manual. Download it now for your reading pleasure.
After you read this technical manual, I’m sure you’ll have many excellent questions. Don’t write to the blogger (me) or put your questions into the blog comments because I cannot answer these sorts of questions and neither can the Xcell Daily blog. Your best bet to get sales and technical questions answered is to immediately contact your friendly neighborhood Xilinx salesperson or FAE.
