You’re going to want to read the new Xilinx 10-page White Paper titled “Pushing Performance and Integration with the UltraScale+ Portfolio” (WP471) by Nick Mehta because this very short document contains some easily found tidbits about Xilinx UltraScale+ devices that might just be essential to the success of your next high-performance system design. These gems are hidden in hundreds of pages of product docs but they’re nicely pulled out for your consideration in this White Paper. For example:
- The enhanced integrated PCIe block has doubled in performance and supports Gen3 x16 and Gen4 x8 (version 0.7)
- The Ethernet MAC/PCS block now incorporates an RS-FEC (Reed-Solomon forward error correction) block, which saves about 100K system logic cells. (You can also use the RS-FEC block as a standalone IP block.)
- The integrated Interlaken block now includes an option to merge two adjacent Interlaken blocks, enabling 300Gbps links using twelve 25Gbps transceivers while saving about 60K system logic cells per 150G Interlaken block.
- You can configure differential I/O pairs as MIPI TX or RX ports to connect with image sensors and DSI (display serial interface) displays.
- Xilinx UltraScale+ devices can interface to DDR4-2667 SDRAMs (and DR3, DDR3L, RLDRAM3, and QDR IV as well).
- Xilinx UltraScale+ devices can also interface to the HMC (Hybrid Memory Cube) at 30Gbps using GTY transceivers.
- DSP slices in UltraScale+ devices can operate at 891MHz. The largest Virtex UltraScale+ FPGA contains nearly 12,000 DSP slices, delivering 21TMACs/sec of fixed-point DSP in one device.
These seven items ought to be enough to interest you in this new White Paper.
