Warning: The following blog post contains graphic references to math in connection with big data analytics. If you are sensitive to or easily put off by algorithmic imagery—equations for example—please skip this one. On the other hand, if you want to see how DRC Computer Corp gets a 100x speed boost in big data analytics, then please read on.
DRC Computer Corp is demonstrating its FPGA-boosted implementation of the Dijkstra and Betweenness Centrality algorithms this week in the Xilinx booth at SC15 in Austin, Texas. (See, I warned you about the math.) To cut to the performance chase, the company is using a 20nm Xilinx Virtex UltraScale VU190 FPGA in conjunction with an IBM POWER8 server and this system is getting a 100x speed boost in algorithmic execution versus a CPU-only implementation while the FPGA consumes only 25W or so. That’s two orders of magnitude speed improvement for very little power and energy consumption.
Just what is the Dijkstra and Betweenness Centrality algorithm? It’s used for graph networking. What’s a graph network? I could try to tell you, but we’re just digging deeper and deeper into the math pit. (See, I really did warn you about the math.) Suffice it to say that graph networking can rapidly identify relationships between people, events, locations, and objects. In other words, it’s an increasingly important big-data-analytics application for many commercial and government organizations, where extremely fast execution can be mission-critical for financial or other reasons.
DRC’s graph networking algorithm uses complex analytics to discover relationships between entities that runs orders of magnitude faster than what can be achieved with conventional computer architectures—and it’s running on Xilinx Virtex UltraScale FPGAs this week at SC15.
Here’s a photo of the system from the Xilinx booth at SC15:
DRC Computer Corp Graph Networking Demo at SC15