If you are concerned about the security of your Zynq-based design, then the new White Paper “Leveraging Asymmetric Authentication to Enhance Security-Critical Applications Using Zynq-7000 All Programmable SoCs” by Ed Peterson should be on your reading list. This White Paper discusses the asymmetric authentication capability built into every Zynq SoC—a capability that protects your design starting with the first bit of the FSBL (first-stage boot loader)—which ensures that only authorized and unmodified data can be loaded into the Zynq SoC(s) you incorporate into your system design. The FSBL is the first piece of user code loaded by a Zynq SoC from an external source. Once loaded, the FSBL is responsible for loading your design’s PS image and PL configuration for the Zynq SoC, so it is extremely important to authenticate the FSBL and to make sure that it has not been modified in any way. These steps initiate a “root of trust” that extends to subsequent loads, which should also be authenticated and decrypted.
The Zynq SoC verifies a digital signature associated with the FSBL using RSA-2048 signature-verification code that resides in the Zynq SoC’s PS BootROM, which is mask-programmed, unchangeable memory. Neither the private nor public RSA-2048 keys are stored on the Zynq SoC. Your manufacturing process permanently programs a 256-bit hash of the public key into the Zynq SoC’s eFUSE array (nonvolatile memory storage) on the device and turns on the authentication feature by programming another eFUSE. You create the public/private RSA key pairs using the Xilinx SDK’s bootgen utility, which is part of the Vivado Design Suite.
This White Paper discusses additional methods for enhancing the security of your Zynq SoC design beyond FSBL authentication including DPS-resistant secure boot, run-time security enhancements, and some 3rd-party security solutions available to you. It also includes an extensive, 16-entry list of references for your further reading enjoyment.
