By Eric Cigan and Noam Levine, MathWorks
In September 2013, MathWorks introduced a hardware-software workflow for Zynq-7000 SoCs using Model-Based Design. In this workflow (Figure 1), designers could create models in Simulink that would represent a complete dynamic system—including a Simulink model for algorithms targeted for the Zynq SoC—and rapidly create hardware-software implementations for Zynq SoCs directly from the algorithm.
System designers and algorithm developers used simulation in Simulink to create models for a complete system (communications, electromechanical components and so forth) in order to evaluate design concepts, make high-level trade-offs, and partition algorithms into software and hardware elements. HDL code generation from Simulink enabled the creation of IP cores and high-speed I/O processing on the Zynq SoC fabric. C/C++ code generation from Simulink enabled programming of the Zynq SoC’s Cortex-A9 cores, supporting rapid embedded software iteration.
The approach enabled automatic generation of the AMBA AXI4 interfaces linking the ARM processing system and programmable logic with support for the Zynq SoC. Integration with downstream tasks—such as C/C++ compilation and building of the executable for the ARM processing system, bitstream generation using Xilinx implementation tools, and downloading to Zynq development boards—allowed for a rapid prototyping workflow.
Central to this workflow are two technologies: Embedded Coder and HDL Coder. Embedded Coder generates production-quality C and C++ code from MATLAB, Simulink and Stateflow, with target-specific optimizations for embedded systems. Embedded Coder has become so widely adopted that when you drive a modern passenger car, take a high-speed train or fly on a commercial airline, there’s a high probability that Embedded Coder generated the real-time code guiding the vehicle. HDL Coder is the counterpart to Embedded Coder, generating VHDL or Verilog for FPGAs and ASICs, and is integrated tightly into Xilinx workflows. This mature C and HDL code generation technology forms the foundation of the Model-Based Design workflow for programmable SoCs.
Design teams using Model-Based Design in applications such as communications, image processing, smart power and motor control have adopted this workflow as the means for algorithm developers to work closely with hardware designers and embedded software developers to accelerate the implementation of algorithms on programmable SoCs. Once the generated HDL and C code is prototyped in hardware, the design team can use Xilinx Vivado IP Integrator to integrate the code with other design components needed for production.
To illustrate the use of this workflow on a common motor control example, consider the case of a field-oriented control algorithm for a three-phase electric motor implemented on a Zynq-7020 SoC (details of this hardware prototyping platform are available at http://www.mathworks.com/zidkhttp://www.mathworks. com/zidk). The motor control system model includes two primary subsystems (Figure 2): a motor controller targeting the Zynq SoC that has been partitioned between the Zynq processing system and programmable logic, and a motor controller FPGA mezzanine card (FMC) connected to a brushless DC motor equipped with an encoder to measure shaft angle.
In Simulink, we can test out the algorithm with simulation long before we start hardware testing. We can tune the PI controller gains, try various stimulus profiles and examine the effect of different processing rates. As we use simulation, though, we face a fundamental issue: Because of the disparate processing rates typical of motor control—that is, overall mechanical response rates of 1 to 10 Hz, core controller algorithm rates of 1 to 25 kHz and programmable logic operating at 10 to 50 MHz or more—simulation times can run to many minutes or even hours. We can head off this issue with a control-loop model that uses behavioral models for the peripherals—the PWM, current sensing and encoder processing—producing the time response shown in Figure 3.
Once performance has been validated with the high-fidelity models, we move on to prototyping the controller in hardware. Following the workflow shown in Figure 1, we start by generating the IP core. The IP core generation workflow lets us choose the target development board and walks us through the process of mapping the core’s input and output ports to target interfaces, including the AXI4 interface and external ports. The next step is to generate embedded C code from the Simulink model targeting the ARM core. The process of generating C code, compiling it and building the executable with embedded Linux is fully automated, and the prototype is then ready to run.
Engineers are turning to Model-Based Design workflows to enable hardware-software implementation of algorithms on Xilinx Zynq SoCs. Simulink simulation provides early evaluation of algorithms, letting designers evaluate the algorithms’ effectiveness and make design trade-offs at the desktop rather than in the lab, with a resultant increase in productivity.
Note: This blog post is an excerpt from a longer and more detailed article appearing in the new Xcell Software Journal, which just went online. You can read the full article, which includes far more detail with an example, by downloading the PDF of this first issue here or clicking here to read the article online.
