SDSoC, Step by Step: Build a Sample Design

2015年9月5日 | By News | Filed in: News.

Source: https://forums.xilinx.com/t5/Xcell-Daily-Blog/SDSoC-Step-by-Step-Build-a-Sample-Design/ba-p/652826

by Adam Taylor, Chief Engineer, e2v

As the PLD’s role has expanded from glue logic to acceleration peripheral and ultimately to the heart of the system, the industry has needed a new design methodology to capitalize on that evolution. In recent years, high-level synthesis (HLS) has become increasingly popular; here, the design is entered in C/C++ (using Xilinx’s Vivado HLS) or tools such as MathWorks’ MATLAB or National Instruments’ LabVIEW. Such approaches begin to move the design and implementation out from the EE domain into the software realm, markedly widening the user base of potential PLD designers and cementing the PLD’s place at the heart of the system as new design methodologies unlock the devices’ capabilities.

It is therefore only natural that SoC-based designs would use HLS to generate tightly integrated development environments in which engineers could seamlessly accelerate functions in the logic side of the design. Enter the SDSoC environment.

The development cycle at the highest abstraction level used in the SDSoC environment is as follows:

  1. We develop our application in C or C++.
  2. We profile the application to determine the performance bottlenecks.
  3. Using the profiling information, we identify functions to accelerate within the PL side of the device.
  4. We can then build the system and generate the SD card image.
  5. Once the hardware is on the board, we can analyze the performance further and optimize the acceleration functions as required.

The environment comes with built-in support for most of the Zynq SoC development boards, including the ZedBoard, the MicroZed, and the Digilent ZYBO Zynq SoC development board. Not only can we develop our applications faster as a result, but we can use this capability to define our own underlying hardware platform for use when our custom hardware platform is ready for integration.

A simple, representative example will illustrate how to accomplish those tasks and reap the resultant benefits. We will target a ZedBoard running Linux and using one of the built-in examples: the Matrix Multiplier and Addition Template. I moved the mmult() function into the hardware after compilation and SD card image generation, running it on my ZedBoard. The execution time (in processor cycles) was only 52,444 / 183,289 = 0.28, or 28% of the previous execution time of 183,289 processor cycles when executed within the PS side of the Zynq SoC. When we consider the performance of the same function when executed within the PS side of the Zynq SoC, we see that we achieve this considerable increase in execution time by a simple click of the mouse.

Note: This blog post is an excerpt from an article appearing in the new Xcell Software Journal, which just went online. You can read the full article by downloading the PDF of this first issue here or clicking here to read the article online.


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