A Double-Barreled Way to Get the Most from Your Zynq SoC

2015年4月3日 | By News | Filed in: News.

Source: http://forums.xilinx.com/t5/Xcell-Daily-Blog/A-Double-Barreled-Way-to-Get-the-Most-from-Your-Zynq-SoC/ba-p/584328

By Adam P. Taylor

(Excerpted and adapted from the latest issue of Xcell Journal)

Many bare-metal applications and simpler operating systems use only one of the two ARM cores in the Zynq SoC’s processing system (PS), a design choice that can potentially limit system performance. Depending upon the application in development, there could, however, be a need to have both processors running bare-metal applications, or to run different operating systems on each of the processors.

Using both of the cores on the Zynq SoC with bare metal or different operating systems is, by definition, an example of asymmetric multiprocessing. AMP on the Zynq SoC can involve any of the following combinations:

  • Different operating systems on Core 0 and Core 1
  • Operating system on Core 0, bare metal on Core 1 (or vice versa)
  • Bare metal on both cores executing different programs

When you decide upon the need to create an AMP system on the Zynq SoC, you must consider the fact that the ARM processor cores contain a mixture of both private and shared resources that must be correctly addressed. Both processors have private L1 instruction and data caches, timers, watchdogs and interrupt controllers (with both shared and private interrupts). A number of shared resources also exist, of which common examples include I/O peripherals, on-chip memory, the interrupt controller distributor, L2 cache and system memory located within the DDR memory. These private and shared resources require careful management.

This blog is a short excerpt from the full article. To read the full article in the latest issue of Xcell Journal with all the technical details, click here.

You might also like to see the many blog posts Adam Taylor has written about using AMP on Zynq SoCs starting with this one:

Adam Taylor’s MicroZed Chronicles Part 46: Using both of the Zynq SoC’s ARM Cortex-A9 Cores


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