UltraScale DDR4-2400 demo shows memory controller timing margins using built-in logic analysis

2015年2月5日 | By News | Filed in: News.

Source: http://forums.xilinx.com/t5/Xcell-Daily-Blog/UltraScale-DDR4-2400-demo-shows-memory-controller-timing-margins/ba-p/562595

This new video (below) demonstrates the use of the Xilinx Vivado 2014.4 Hardware Manager for Memory Interface Generator (MIG) IP designs to create, install, and test a DDR4-2400 memory controller in a Xilinx Virtex UltraScale VU095 FPGA on a VCU107 eval board.

The memory controller drives an 80-bit-wide bank of DDR4-2400 SDRAM on the eval board. It runs a calibration cycle on the DDR4 SDRAM and the video then looks at the timing results and the resulting timing margins from the calibration cycle to make sure that the timing has been correctly centered in the data-valid windows for each bit. The calibration cycle is critical to ensuring proper memory operation over PVT (process variation, voltage variation, and temperature variation) for both the rising and falling edges of the memory clock. The video ends with a look at the integrated in-circuit logic analyzer—an IP core that integrates easily with the Vivado Design Suite—which provides an on-screen view of memory read and write cycles to ensure error-free operation.

Here’s the video:

(Be sure to run the video full screen if you want to read what’s on the Vivado displays.)


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