By Adam Taylor
When we looked at the Zynq SoC’s AXI DMA last week, I explained how we could use an AXI DMA controller to move data from the PL to the PS. In this blog we will look at how we build hardware to do this.
The first thing to do is to understand a little more about the AXI streaming interface. The Vivado Design Suite AXI Reference Guide (User Guide 1037) rather helpfully provides detailed information on the the Zynq SoC’s AXI protocols. To create hardware for this example we will be using:
- AXI4-Stream – High performance output from the Zynq SoC’s XDAC streaming to memory mapped port using DMA
- AXI4-Lite – To configure and control the XADC and the DMA controller
- AXI4 – To configure the FIFO adapter
These various uses will require two separate AXI buses—one that the PS controls as the master and another in which the PS is the slave.
The master PS AXI interconnect allows the PS to configure and control the XADC and DMA controller. These devices must be configured before transfers can occur. The slave PS AXI port allows the XADC data to be streamed and converted by the AXI DMA controller into a format suitable for memory-mapped transactions. The DMA is capable of transmitting data in either direction using these ports:
- S/M_AXIS_S2MM – Slave/Master stream to memory map (device to DMA)
- S/M_AXIS_MM2S – Slave / Master memory map to stream (DMA to device)
However due to a slightly different implementation of the AXI interface, the DMA controller requires the use of the optional input TLast. The XADC and the AXI DMA module cannot be directly connected, so an interface adapter is required to drive the optional TLast pin. Such an adapter already exists within the example code provided by XAPP1183 (“Implementing Analog Data Acquisition using the Zynq-7000 AP SoC Processing System with the XADC AXI Interface”). It is therefore rather straightforward to download the code example and add in the hard IP adapter to our IP catalog in Vivado.
With the IP adapter added to the IP catalog, we can easily insert this block between the XADC and the DMA port to create a hardware design as below:
For this example, I have connected the DMA S2MM master output to the slave GP AXI input on the PS, which allows us to store the data in either OCM (on-chip memory) or off-chip DDR SDRAM. GP AXI is the correct interface to use here due to the required data transfer rates from the XADC.
While the DMA in this example only transfers data in one direction S2MM, the MM2S ports are there if transfer is needed in the other direction. These can be removed by customising the core and disabling the read channel.
In the next blog we will look at the software we need to drive this hardware.