The Hybrid Memory Cube Consortium (HMCC) rolled out the HMCC 2.0 interface specification for the Hybrid Memory Cube late last month. Notably, HMCC 2.0 raises the maximum per-lane data rate from 15 to 30Gbps. That makes it a good time to point out that the Xilinx Virtex UltraScale VU095 FPGA that started to ship to customers last May has 32 on-chip GTY transceivers capable of 32.75Gbps operation. Xilinx demonstrated HMC compatibility at SC14 in New Orleans last month using the Open-Silicon HMC controller IP. (See “Want to see the Micron HMC (Hybrid Memory Cube) transfer 40+Gbytes/sec? Watch the demo video from SC14.”) There appears to be no major obstacle in scaling this IP to meet the new HMC 2.0 spec.
Here’s the video of the HMC demo at SC14, in case you missed it.