Configure an UltraScale FPGA in less than 200msec. (This works for Xilinx 7 series FPGAs too!)

2014年12月11日 | By News | Filed in: News.

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XAPP1220, “UltraScale FPGA BPI Configuration and Flash Programming” by Stephanie Tapp and Ryan Rumsey, tells you how to use parallel x16 NOR Flash memory connected to a Xilinx Virtex UltraScale FPGA’s master byte peripheral interface (BPI) to get blazing-fast device configuration. How fast? Well, how about 199.13msec for reading all 286,746,912 configuration bits into a Xilinx Virtex UltraScale VU095 device? That’s the result obtained when running the NOR Flash memory’s clock at 90MHz. (The Virtex UltraScale FPGA’s maximum rate on the BPI port is actually 111MHz). Flash programming times are also comparatively quick using the FPGA’s JTAG port to send the programming data to the BPI-attached NOR Flash through the FPGA. Here’s a diagram of the connection between the FPGA and a Micron NOR Flash memory:

 

 

UltraScale FPGA to NOR Flash Connection Diagram.jpg

 

 

XAPP1220 explains how to program the Flash memory using the Xilinx Vivado Design Suite tools. The Micron NOR Flash memory starts in asynchronous read mode by default. XAPP1220 walks you through the steps needed to prepare a NOR Flash programming file using Vivado tools so that the resulting bitstream configures the NOR Flash memory for synchronous burst-mode transfers. Note that if you don’t configure the Flash memory for burst mode transfers, then you lose more than 90% of the technique’s performance. This technique works for all Xilinx FPGAs based on the UltraScale architecture. You should note that Xilinx 7 series FPGAs also have BPI ports that can deliver fast configuration times, as described in XAPP587, BPI Fast Configuration and iMPACT Flash Programming with 7 Series FPGAs.

 

Two additional items of note:

 

  1. XAPP1220 discusses this technique using the Vivado Design Suite while XAPP587 employs the Xilinx ISE Design Suite.
  2. XAPP1220 discusses this technique for using Vivado to configure the Flash memory for Xilinx UltraScale All Programmable devices but it applies equally well to 7 series devices.

 

 

 

 

 


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