New UltraScale pcb user guide gives advice on connecting FPGAs to DDR3 and DDR4 SDRAMs

2014年12月6日 | By News | Filed in: News.

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The newly revised Xilinx UltraScale Architecture PCB Design User Guide (UG583) gives you many deisgn tips for laying out printed-circuit boards for Xilinx UltraScale All Programmable devices in its 122 pages. Though certainly not limited to connections for memories, I found the information for connecting DDR3 and DDR4 SDRAMs especially interesting. For example, here are illustrations from the guide for DDR3 address and clock terminations:

 

 

 DDR3 Address Termination.jpg

 

 

 

DDR3 Clock Termination.jpg

 

 

 

Contrast this with the illustrations from the guide for DDR4 address, command, control, and clock terminations:

 

 

DDR4 Address Command and Control Termination.jpg

 

 

 

 

DDR4 Clock Termination.jpg

 

 

 

 

 


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