If you’re interested in working with the Micron HMC (Hybrid Memory Cube), then you’ll likely be interested in openHMC—an open-source, AXI4-compliant memory controller for the HMC developed by the Computer Architecture Group at the University of Heidelberg in Germany. It’s a parameterizable IP block that allows you to set different overall data widths, external lane widths, and clock speeds depending on application needs. Micron was exhibiting an HMC board connected to a Xilinx UltraScale FPGA eval board implementing the open-source HMC controller in its booth at SC14 (Supercomputing 14) in New Orleans.
The openHMC memory controller implements the following features as described in the HMC specification Rev 1.1:
- Full link-training, sleep mode, and link retraining
- 16- to 128-byte read and write (posted and non-posted) transactions
- Posted and non-posted bit-write and atomic requests
- Read and Write Mode
- Full packet flow control
- Packet integrity checks (sequence number, packet length, CRC)
- Full link retry
Currently the following configurations are supported (8 or 16 lanes):
- 2 FLITs per Word / 256-bit datapath
- 4 FLITs per Word / 512-bit datapath
- 6 FLITs per Word / 768-bit datapath
- 8 FLITs per Word / 1024-bit datapath
For more information and a free Verilog download of the open-source IP, click here.