By William D. Richard, Associate Professor, Washington University, St. Louis
Upsampling is required in many signal-processing applications. The easiest way, conceptually, to upsample a vector of data by a factor of M is to zero-pad the discrete Fourier transform (DFT) of the data vector with (M-1) times as many zeros as there are actual frequency components and then transform the zero-padded vector back into the time domain. This approach is computationally expensive, however, and does not lend itself to efficient implementation inside FPGAs. The efficient, parallel, real-time upsampling circuit presented here produces M upsampled values per ADC clock, where M is the desired upsampling factor. Our Xilinx Virtex-6 XC6VLX75T FPGA implementation, which upsamples by a factor of M=4, serves as an example of the more general technique.