9 quick bullets on the Xilinx UltraScale Architecture, Virtex and Kintex UltraScale FPGAs, and Vivado’s latest release

2014年11月4日 | By News | Filed in: News.


The latest issue of Xcell Journal, released last week, carries an UltraScale overview written by Nick Mehta. (See “Productivity Skyrockets with Xilinx’s UltraScale Architecture.”) Here are some key points about Virtex UltraScale and Kintex UltraScale FPGAs and the Vivado Design Suite extracted from Mehta’s article:



  • Data is transported to and from FPGAs based on the UltraScale architecture through a combination of the high-performance parallel SelectIO and high-speed serial transceiver connectivity. The different serial transceivers in the UltraScale architecture transfer data at up to 16.3 Gbps, providing all the performance required for mainstream serial protocols, and at up to 32.75 Gbps, enabling 25G+ backplane designs with dramatically lower power per bit than previous-generation transceivers. All transceivers in UltraScale FPGAs support the required data rates for PCI Express® Gen3 and Gen4, and integrated blocks for PCI Express enable FPGAs based on the UltraScale architecture to support up to x8 Gen3 Endpoint and Root Port designs.

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