Secrets of the UltraScale architecture’s DDR4 SDRAM interface

2014年10月30日 | By News | Filed in: News.

Adrian Cosoroaba and Terry Magee gave a detailed presentation on the DDR4 SDRAM interface designed into the new Xilinx UltraScale All Programmable FPGAs at MemCon earlier this month. This interface is designed to take DDR SDRAM to 2400Mbps and beyond while lowering the interface power consumption. To do this, the Xilinx engineers had to turn the DDR4 interface problem on its head. Instead of designing DDR4 capability into the UltraScale I/O PHYs, they designed a DDR4 I/O PHY from the ground up and then expanded its abilities to support other I/O requirements. The result: a basic 13-bit programmable byte lane that’s first and foremost a DDR4 PHY.


If you’re coming from the SoC world, it might not be obvious why Xilinx has taken this approach. It’s because I/O pins are a scarce resource. While there are hundreds of thousands or millions of logic cells and flip-flops, multiple Mbits of block RAM, and thousands of DSP slices, there are only a few hundred I/O pins due to physical package limitations. Thus the I/O pins must be programmable and flexible enough to cover any possible I/O use ranging from driving banks of DDR4-2400 SDRAM to blinking an LED and pretty much everything in between. For UltraScale architecture FPGAs, it made sense to do the hard portion of the I/O design first—the DDR4 PHY—and then add in the easier stuff.

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