Battle Royale—High-Performance Packet Processing with FPGAs, NPUs, or Multicore Processors? Next week at Linley Processor Conference

2014年10月10日 | By News | Filed in: News.

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Do you need a clear understanding of the advantages and disadvantages of FPGAs, NPUs, and Multicore CPUs for packet processing? You will get one at next week’s Linley Processor Conference 2014 in Santa Clara. Atul Shinde from Xilinx will be speaking about “Partitioning Hardware and Software Programmability for Best Carrier Ethernet Processing” on the first day of the conference, October 22, and I’ve stolen the following slide from his slide deck as a taste of what he’ll be discussing:

 

 Packet Processing Programmability Comparison.jpg

 

 

Shinde’s slide lists five major dimensions for the purpose of comparison:

 

  1. Description portability: You face extra work if you need to change your system description to fit the implementation hardware.
  2. Packet processing flow: If the implementation hardware does not match the natural flow required for packet processing, you face bottlenecks and resource conflicts.
  3. Lookup tables: Fixed-size memories in a hardware implementation lead to wasted resources and access conflicts.
  4. QoS policies: Poor implementation granularity leads to sub-optimal scaling and a lack of needed flexibility.
  5. Proprietary IP: If your packet processing requires anything special, you’ll incur additional hardware or suffer the inefficiency of software-based processing using NPUs or Multicore CPUs.

 

Don’t believe it? Register for the conference and make Shinde prove it to you.

 

Registration for pre-qualified attendees is free if registration forms are received by October 16, 2014. Registration for non-qualified attendees is $795 if received by that date. On-line registration closes on Thursday, October 16 at 5 PM Pacific.

 


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