Learn to debug and validate DDR3/DDR4 SDRAM designs in 1-day Keysight class, Oct 21 in Santa Clara

2014年10月8日 | By News | Filed in: News.

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Looking down the barrel of a DDR4-2400 or a fast DDR3 SDRAM design? Want some help? Keysight (formerly the T&M piece of Agilent) is giving a free, 1-day design seminar titled “Gain insight into DDR3/4 and LPDDR3/4 Signal Flow” in Santa Clara, California on October 21. This is a live class and promises to be well work a day of your time. It’s being taught by Jennie Grosslight, Keysight’s Memory Test Product Manager. I met her at DesignCon earlier this year. (See “Avoid the three pitfalls of designing with DDR4 SDRAM – Live from DesignCon 2014.”) If I was going to design a DDR4-baseed design, I’d want Jennie’s help. If you attend this class, you’ll understand why.


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