Eliminate an EPROM in your system design by booting processor and FPGA from the same memory using as few as 2 pins

http://ift.tt/ZI8xMi

A new Xilinx App Note, XAPP1188—FPGA Configuration from SPI Flash Memory using a Microprocessor, tells you how to use the same EEPROM to hold your processor’s boot code and your FPGA’s configuration bitstream. This approach obviously reduces component count and you can implement this idea using as few as two SPI pins: MISO and SCLK. The application note describes several scenarios using two pins and up. One of them just might fit your needs.

 

 

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