INVEA-TECH and CESNET (the Czech Republic’s National Research and Education Network) have demonstrated a method for sustaining data transfer from a 100Gbps Ethernet port to a host CPU using two of an FPGA’s PCIe Gen 3 x8 interface ports in parallel. The concept is called bifurcation and it was introduced on Intel’s Core I7 CPUs a couple of years ago. Intel’s intent was to allow splitting of the CPU’s PCIe x16 ports so that they could handle two separate tasks but the technique works just as well when used in reverse: to merge two external PCIe x8 ports into one x16 port. Using bifurcation to build a 100Gbps system with a single FPGA eliminates the need for an additional PCIe switch chip, which saves cost, board space, and approximately 6W of power.
CESNET and INVEA-TECH conducted a series of experiments to demonstrate the benefits of PCIe bifurcation. The test setup included a custom FPGA card equipped with a Xilinx Virtex-7 H580T 3D FPGA. Two of the FPGA’s PCIe x8 hard blocks were connected to a PCIe x16 slot on the card. The FPGA firmware working in concert with Linux device drivers transferred data to a ring buffer located in the PC’s RAM. The PCIe x8 interfaces were used in a round-robin manner to transfer data to a single buffer. The following block diagram illustrates the experimental setup: