In FPGA Design, Timing Is Everything

2014年7月29日 | By News | Filed in: News.

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By Angela Sutton, Staff Product Marketing Manager, FPGA, Synopsys and Paul Owens, Corporate Applications Engineer, FPGA, Synopsys

 

 

When your FPGA design fails to meet timing performance objectives, the cause may not be obvious. The solution lies not only in the FPGA implementation tools’ talent in optimizing the design to meet timing, but also in the designer’s ability to specify goals upfront and diagnose and isolate timing problems downstream. Designers now have access to certain tips and tricks that will help you set up clocks; correctly set timing constraints using tools like Synopsys Synplify Premier; and then tune parameters to meet the performance goals of your Xilinx FPGA design.


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