By Kimon Karras, Research Engineer and James Hrica, Senior Software Applications Engineer, Xilinx
Designers have used HLS (high-level synthesis) for video and signal processing with considerable success. HLS lets you use a high-level programming language to express hardware functionality. To test how the technology would work with packet processing, we built a prototype system completely with the Xilinx Vivado HLS tool, producing really exciting results. Vivado HLS halved our development time, reduced the resources we used, and lowered latency. Our example system was a simple ARP/ICMP server that replies to ping and Address Resolution Protocol (ARP) requests and resolves IP address queries.
Vivado HLS provides tangible benefits for designers by raising the abstraction level of system design. It does this in two main ways:
- Utilizing C/C++ as a programming language and leveraging the high-level constructs available in such a language
- Providing additional data primitives, which allow the designer to easily use basic hardware building blocks (bit vectors, queues, etc.)
These characteristics allow a designer using Vivado HLS to tackle common protocol system design hurdles much more easily than when using RTL, which eases system assembly, simplifies FIFO and memory access, and enables abstraction of the control flow. Easy architectural exploration and simulation are other major benefits of this technology.