TCP and UDP Session Hardware Accelerator supports 16K concurrent sessions on VC707 dev board

2014年7月12日 | By News | Filed in: News.

Intelop has ported its 10G TCP and UDP Offload Engine (TOE/UOE) to the VC707 dev board based on a Xilinx Virtex-7 XC7VX485T FPGA. The Intelop TOE/UOE implemented with an FPGA supports as many as 16K simultaneous TCP and UDP connections and unlimited continuous connections on 10G Ethernet ports with ultra-low latency (sub 100nsec) and zero jitter regardless of the number of connections. The entire TOE/UOE subsystem consumes fewer than 12K slices and 4Mbytes of BRAM. Integration of the pretested Intelop TOE/UOE on an FPGA-based eval board permits immediate experimentation and customization for specific networking applications.



 Intelop TOE UOE on Xilinx VC707 Eval Board.jpg

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